This invention relates in general to a semiconductor integrated circuit device and to the method of its fabrication; and, in particular, the invention relates to a semiconductor integrated circuit device having an MISFET (metal-insulator-semiconductor field-effect transistor) with p-type-conductive silicon gate electrodes.
N-type silicon gate electrodes are normally used in a CMOS (complementary metal-oxide semiconductor) device in which n-channel MISFETs and p-channel MISFETs are formed in the same substrate. In this type of CMOS device, the n-channel MISFETs are often in the surface channel configuration with the p-channel MISFETs in the embedded-channel configuration.
When, however, as processes of fabricating semiconductor integrated circuit devices continually become finer, a designing process with a fineness of 0.2 xcexcm or narrower is applied to the p-channel MISFET, it is suspected that the embedded-channel configuration will be insufficient in terms of preventing the short channel effect. The p-channel MISFET will thus have to be provided in the surface-channel configuration with p-type silicon gate electrodes. A CMOS device in the so-called dual-gate configuration, which comprises an n-channel MISFET with n-type silicon gate electrodes and a p-channel MISFET with p-type silicon gate electrodes, is being considered.
P-type impurities, such as boron (B), are implanted in the p-type silicon gate electrode. However, since boron has a high diffusion coefficient in the gate-insulating film, boron may encroach into the substrate of the p-channel MISFET and cause a change in the concentration of boron in the channel region. The threshold voltage of the MISFET is thus shifted, its avalanche breakdown voltage deteriorates, and its operating characteristics will be broadly dispersed.
A method for preventing the shift in the threshold voltage caused by the change in the concentration of boron in the channel region has been disclosed in Official Patent Gazette H.6-275788. Boron ions are implanted into an n-type polysilicon film, into which n-type impurities have been uniformly placed, to convert the film into p-type polysilicon. The gate electrodes are then formed by patterning this polysilicon film. After that, impurities are implanted into the substrate with the gate electrodes acting as masks for self-alignment. Here, since the activation temperature of the implanted impurities is set rather low, in the range from 800 to 900xc2x0 C., the diffusion of boron is prevented.
The inventors, however, have found that when boron ions are implanted in the polycrystalline silicon film, boron atoms reach the gate-insulating film and even the interface with the substrate by the channeling effect. The result is a change in the concentration of boron in the channel region.
Moreover, when the gate electrodes are used as masks for the self-aligned implantation of impurities in the substrate, the impurities are simultaneously implanted in the polycrystalline silicon film, which configures the gate electrodes. The threshold voltage would then be expected to change and cause deterioration in the reproducibility of the MISFET""s operating characteristics.
The object of this invention is to provide a technique that can obtain the desired operating characteristics for an MISFET with p-type silicon gate electrodes.
The foregoing object and novel features of this invention will be clarified by the following specification together with the accompanying drawings.
A typical example of the invention disclosed in this application is briefly summarized in the following.
(1) The semiconductor integrated circuit device of this invention having an MISFET comprises:
a gate-insulating film located on the substrate;
gate electrodes, which are located on the gate-insulating film and constructed of the p-type polycrystalline silicon film, in which p-type impurities and n-type impurities have been implanted;
an insulating film, which is located over the p-type polycrystalline silicon film and has the same flat form as the p-type polycrystalline silicon film; and
the source and drain of a p-channel or of an n-channel, which are located in the substrate on both sides of the gate electrode.
The method of fabricating a semiconductor integrated circuit device of this invention, when forming an MISFET with p-type silicon gate electrodes, comprises the steps of:
forming a gate-insulating film on the surface of the substrate;
depositing an amorphous silicon film on the gate-insulating film;
forming an n-type amorphous silicon film by ion-implanting n-type impurities in the amorphous silicon film;
converting the n-type amorphous silicon film into a p-type amorphous silicon film by ion-implanting p-type impurities in the n-type amorphous silicon film;
converting the p-type amorphous silicon film into a p-type polycrystalline silicon film by a process of crystallization;
forming gate electrodes by etching the insulating film, which has been deposited on the p-type polycrystalline silicon film immediately before this process, and p-type polycrystalline silicon film in turn; and
forming a semiconductor region in which the source and drain are to be constructed.
Referring to the method described above, implanting the n-type impurities in the p-type polycrystalline silicon film, of which the gate electrodes are constructed, prevents the diffusion of the p-type impurities, such as boron, which have been injected in said p-type polycrystalline silicon film. This prevents changes in the concentration of boron in the channel region.
Again referring to the method described above, the channeling effect is prevented by implanting the n-type impurities and p-type impurities in the amorphous silicon film, which has been deposited over the gate-insulating film. As a result, changes in the concentration of boron in the channel region which are caused by the ion-implanted impurities reaching the gate-insulating film and even the interface with the substrate, are prevented.
Again referring to the method described above, the concentration of impurities in the p-type polycrystalline silicon film, of which the gate electrodes are constructed, and the concentration of impurities in the semiconductor region, of which the source and drain are constructed, are optimized independently. As a result, the optimal device configuration for an MISFET can easily be provided.